Description of the NMRA-DCC Loco Decoder with ATtiny15

Programming and readable in DIR, PAG, REG, BIT mode and programming on main.
The front and rear lights are depending from the drive direction and cannot be reprogrammed (FL & RL). But there is an additional function implemented. If there is a need of two functions without light the two output ports of the light (FL, RL) can be connected to produce one independent function.

The back EMF has experimental statium (CV58).
The PWM frequency and scale can be controlled via CV59 and CV60.


CV59 - PWM Frequenz (Timer/Counter1 Control Register TCCR1)
PWM frequency (113-127, 01110001-01111111), 112=off 128=on, non inv. PWM (97-111, 01100001-01101111)

Bit 7 CTC1: Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A Register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

Bit 6 PWM1: Pulse Width Modulator Enable
When set (one), this bit enables PWM mode for Timer/Counter1. This mode is described on page 31.

Bits 5,4 COM1A1, COM1A0: Compare Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.

Bits 3, 2, 1, 0 CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

0000Timer/Counter1 is stopped.
0001CK*16 (=PCK)
0010CK*8 (=PCK/2)
0011CK*4 (=PCK/4)
0100CK*2 (=PCK/8)
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK oscillator clock.

CV60 - PWM Auflösung (Timer/Counter Output Compare Register OCR11)

The Timer/Counter Output Compare Register 1A contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match occurs only if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set (one) the Compare Interrupt Flag in the CPU clock cycle following the compare event.

Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A (OCR1A) form an 8-bit, free-running and glitch-free PWM with outputs on the PB1(OC1A) pin. Timer/Counter1 acts as an up-counter, counting up from $00 up to the value specified in the second Output Compare Register OCR1B, and starting from $00 up again. When the counter value matches the contents of the Output Compare Register OCR1A, the PB1(OC1A) pin is set or cleared according to the settings of the COM1A1/COM1A0 bits in the Timer/Counter1 Control Registers TCCR1. Refer to Table 12 for details.

Timer/Counter1 Output Compare RegisterB OCR1B
The Output Compare Register1 (OCR1B) is an 8-bit read/write register. This register is used in the PWM mode only, and it limits the top value to which the Timer/Counter1 keeps counting. After reaching OCR1B in PWM mode, the counter starts from $00.
The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value + 1.

Clock SelectionOCR1BPWM Frequency
CK15910 kHz
CK15910 kHz
PCK/815920 kHz
PCK/421330 kHz
PCK/415940 kHz
PCK/225550 kHz
PCK/221360 kHz
PCK/218170 kHz
PCK/215980 kHz
PCK/214190 kHz
PCK255100 kHz
PCK231110 kHz
PCK213120 kHz
PCK195130 kHz
PCK181140 kHz
PCK169150 kHz

Followed CV's are implemented:

cv1 1-127 ;Primary Address
cv2 0-255 ;Vstart
cv3 0-255 ;Acceleration Rate
cv4 0-255 ;Deceleration Rate
cv5 0-255 ;Vhigh
cv6 0-255 ;Vmid

cv33 =6 ;(Forward Headlight)
cv34 =7 ;(Reverse Headlight)
cv35 =8 ;(Function 1)
cv36 =9 ;(Function 2)
cv37 =10 ;(Function 3)
cv38 =11 ;(Function 4)
cv39 =12 ;(Function 5)
cv40 =13 ;(Function 6)
cv41 =14 ;(Function 7)
cv42 =15 ;(Function 8)

cv17 =16 ;Extended Address low
cv18 =17 ;Extended Address high
cv19 =18 ;Consist Address

cv29 =19 ;Configuration Data #1

.............Manufacturer Unique..............
cv52 =20 ;
cv53 =21 ;
cv54 =22 ;
cv55 =23 ;(Vmax 2)
cv56 =24 ;
cv57 =25 ;
cv58 =26 ;Back EMF
cv59 =27 ;PWM frequency (113-127), 112=off 128=on, non inv. PWM ( 97-111)
cv60 =28 ;PWM scale
cv61 =29 ;
cv62 =30 ;
cv63 =31 ;
cv64 =32 ;(configuration byte)

cv65 =33 ;Kick Start
cv66 =34 ;Forward Trim
cv67 =35 ;Speed Table 1
cv68 =36 ;Speed Table 2
cv69 =37 ;Speed Table 3
cv70 =38 ;Speed Table 4
cv71 =39 ;Speed Table 5
cv72 =40 ;Speed Table 6
cv73 =41 ;Speed Table 7
cv74 =42 ;Speed Table 8
cv75 =43 ;Speed Table 9
cv76 =44 ;Speed Table 10
cv77 =45 ;Speed Table 11
cv78 =46 ;Speed Table 12
cv79 =47 ;Speed Table 13
cv80 =48 ;Speed Table 14
cv81 =49 ;Speed Table 15
cv82 =50 ;Speed Table 16
cv83 =51 ;Speed Table 17
cv84 =52 ;Speed Table 18
cv85 =53 ;Speed Table 19
cv86 =54 ;Speed Table 20
cv87 =55 ;Speed Table 21
cv88 =56 ;Speed Table 22
cv89 =57 ;Speed Table 23
cv90 =58 ;Speed Table 24
cv91 =59 ;Speed Table 25
cv92 =60 ;Speed Table 26
cv93 =61 ;Speed Table 27
cv94 =62 ;Speed Table 28
cv95 =63 ;Reverse Trim

Wiring Diagram:

Corrected Board Layout: