/*
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
    published by the Free Software Foundation; either version 2 of
    the License, or (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

	NMRA ACCESSORY DCC Decoder for ATMEL AtTiny45.
	(C) 2007, Heiko Schroeter
	Samples are taken every 21us interupt driven by timer0.
	Achtung: Auch in Makefile anpassen !
*/

#define ATTiny45
 
  /*
    F_CPU declared here because it is needed for delay.h
  */
#define F_CPU 8000000
 
#include <stdio.h>
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
#include <avr/eeprom.h>
#include <inttypes.h>
#include <util/delay.h>
#include "attiny45_accessory_014.h"
 
 
/****************** INTERRUPT CAPSULATION *************************************/
 
void prmbl ()
{
  if(samples >= 0)
    {
      numbits = 0;  // No Zero allowed in PREAMBLE
    }
  else
    {
      if(numbits >= NumPrmbl)
	{
	  state++; // Advance if we have enough 'ones'
	}
      numbits++;
    }
}
 
void wtlo ()
{
  if(samples >= 0) // Advance if ZERO received
    state++;
}
 
void tstlo ()
{
  if(samples < 0) // A ONE signals end of DCC command
    {
      if(config & (1<<EndOfData)) // End of DCC stream. Go decoding
	{
	  config |= (1 << GoDecode);
	}
    }
  else
    {
      state = 3;   // Get ready for next DCC Byte
    }
}

void bit22 ()
{
  if(samples >= 0)  // check if second half = first half, otherwise error
    {
      if(bitrec & (1<<0)) state=0xFF; // Reset state=0 if not equal
    }
  else
    {
      if(!(bitrec & (1<<0))) state=0xFF; // Reset state=0 if not equal
    }
  state++;
}

void bit12 ()
{
  if(samples >= 0)
    {
      CLC(); // Clear Carry -> ZERO received
    }
  else
    {
      SEC(); // Set Carry   -> ONE received
    }
  ROL(bitrec);  // Move received BIT into data container
  state++;      // Advance state
}
 
void wtxlo ()
{ 
  
  //  We have to semaphore end of DCC Command, because of Interrupt driven reception.
  //  Jump to decode has to happen in main loop.
  if(numbytes > MaxNumBytes - 1)
    {
      numbytes = MaxNumBytes - 1;
    }
  dcc_data[numbytes] = bitrec;  // Save the received byte
  numbytes++;                   // Count the bytes received
  state++;                      // Advance state
  if(samples < 0)               // If a DCC One here, than End of DCC packet
    {
      config |= (1<<EndOfData);    // Semaphore End of DCC Command in stream
    }
}
 
 
ISR(TIM0_COMPA_vect)
{
  
  // Save Level at DCCIN in T to croos the following IF statement. Don't change !
  asm volatile ("bst %0,%1" :: "r" (PINB), "i" (DCCIN));
  
  // Check if DCCIN = LastLevel sampled. If not -> analyze DCC stream, else keep on sampling.
  if((SREG & _BV(SREG_T) && (!(config & (1<<LastLevel)))) ||
     (!(SREG & _BV(SREG_T)) && (config & (1<<LastLevel))))
    {
      // Save Level for next round. Don't change !
      asm volatile ("bld %0,%1" :: "r" (config), "i" (LastLevel));
      switch(state)
	{
	case 0:       // DCC Preamble state
	  prmbl();
	  break;
	case 1:       // Wait for first ZERO half. Startbit
	  wtlo();
	  break;
	case 2:       // Check second Zero halfbit
	case 20:
	  tstlo();
	  break;
	case 3:       // Get first half of a DCC data Bit
	case 5:
	case 7:
	case 9:
	case 11:
	case 13:
	case 15:
	case 17:
	  bit12();
	  break;
	case 4:       // Get second half of a DCC data Bit
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
	case 16:
	case 18:
	  bit22();
	  break;
	case 19:      // Check for DCC packet termination Bit
	  wtxlo();    // ZERO = get next DCC Byte, ONE = go decoding
	  break;
	default:      // Paranoia safety
	  break;
	}
      samples = Abtast;  // Reset sample counter.
    }
  else
    {
      // Every 35us approx. we jump here
      // 10ms -> 285 times
      // 30ms -> 857 times
      
      // Save Level for next round. Don't change !
      asm volatile ("bld %0,%1" :: "r" (config), "i" (LastLevel));
      // Increment the DCC stream samples
      samples++;
    }
}
 
/****************** END INTERRUPT CAPSULATION *********************************/
 
 
/****************** NO INT HERE ***********************************************/
 
void acknowledge(void)
{
  unsigned char temp = PORTB;
  // Acknowledge
//  SET_ACKMASK;
  PORTB = 0xFF;
  _delay_ms(50);
  _delay_ms(50);
  _delay_ms(50);
//  CLR_ACKMASK;
  PORTB = temp;
}
 
/* RP 9.21
   Extended Accessory Decoder Control Packet Format
   The Extended Accessory Decoder Control Packet is included for the purpose of transmitting aspect control to signal
   decoders or data bytes to more complex accessory decoders. Each signal head can display one aspect at a time.
   {preamble} 0 10AAAAAA 0 0AAA0AA1 0 000XXXXX 0 EEEEEEEE 1
   XXXXX is for a single head. A value of 00000 for XXXXX indicates the absolute stop aspect. All other aspects
   represented by the values for XXXXX are determined by the signaling system used and the prototype being
   modeled.
 
   {preamble} 0 10AAAAAA 0 0AAA0AA1 0 000XXXXX 0 EEEEEEEE 1
   43210
   Bit4: On(1)/Off(0)
   Bit3-0: Number of Function
*/
 
 
/*
  Extended Decoder Control Packet address for operations mode programming
  10AAAAAA 0 0AAA0AA1
  Please note that the use of 0 in bit 3 of byte 2 is to ensure that this packet cannot be confused with the legacy
  accessory-programming packets. The resulting packet would be:
  {preamble} 10AAAAAA 0 0AAA0AA1 0 (1110CCVV 0 VVVVVVVV 0 DDDDDDDD) 0 EEEEEEEE 1
  Signal Decoder Address (Configuration Variable Access Instruction) Error Byte
 
  11Bit-Address as following
  AAA    AAAAAA                AA
  |||    Bit0-5 in Byte1       Bit1&2 in Byte2
  |||
  |||
  |||_
  ||__\ Complement and store in Byte2 Bit4-6
  |___/
  Complementing and Bit fiddling is done in Service Mode.
  Therefore we can check Byte1 and Byte2 directly during transmission.
 
*/
 
void decode_packet_acc()
{
  // 11Bit extended Accessory Decoder
  unsigned char temp;
  unsigned char temp1;
 
  switch(dcc_data[2] & 0xE0)
    {
    case 0:
      temp = dcc_data[2];
      if(((temp & 0xF) <= NumIoPins) && (temp & (1<<4)))  // {preamble} 0 10AAAAAA 0 0AAA0AA1 0 000XXXXX 0 EEEEEEEE 1
	CVs_ram[(temp & 0xF) + PioConfig] |= (1 << PORTSTATUS); // Semaphore On
      else
	CVs_ram[(temp & 0xF)] &= ~(1 << PORTSTATUS); // Semaphore Off
      
      config &= ~((1<<RstFlag) | (1<<SmPkt)); // Clear Semaphores if you came here
      break;
      
    case 0xE0:
      // {preamble} 10AAAAAA 0 0AAA0AA1 0 (1110CCVV 0 VVVVVVVV 0 DDDDDDDD) 0 EEEEEEEE 1
      switch((dcc_data[2] & 0xF) >> 2)
	{
	  /*
	    The defined values for Instruction type (CC) are:
	    CC=00 Reserved for future use
	    CC=01 Verify byte
	    CC=11 Write byte
	    CC=10 Bit manipulation
	  */
	case 0:
	  break;
	case 1: // Verify
	  temp = cv2sram_offset(dcc_data[3] + 1);   //???????????????????
	  if(!(dcc_data[4] = eeprom_read_byte(&temp)))
	    acknowledge();
	  break;
	case 2:
	  break;
	case 3: // Write
	  temp = cv2sram_offset(dcc_data[3] + 1);
	  if(temp == 1) // CV1 --> Bits 2-7 as 0-5 in CV1, Bits0&1 as 1&2 in CV9 
	    {
	      temp  = (dcc_data[4]>>2) & (1<<7) & ~(1<<6);
	      temp1 = ((((dcc_data[4] & 0x3) << 1) & ~(1<<3)) | (1<<0));
	      eeprom_write_byte(&temp,1);
	      eeprom_write_byte(&temp1,9);
	    }
	  else if(temp == 9) // CV9 --> 3MSB complemented in Bits 4-6
	    {
	      temp = cv2sram(9);
	      temp = eeprom_read_byte(&temp) & 0xF0;
	      temp1 = (~(dcc_data[4] >> 4)) & 0xF0;
	      temp  = temp | temp1;
	      eeprom_write_byte(&temp,9);
	    }
	  else
	    {
	      eeprom_write_byte(&dcc_data[4],temp);
	    }
	  acknowledge();
	  break;
	default:
	  break;
	}
      break;
 
    default:
      break;
    }
}
 
 
void decode_packet_multi()
{
  unsigned char temp1;
  unsigned char temp = (dcc_data[1] & 0xE0); // Isolate DCC command
  // Jump now DCC command routine
  switch(temp)
    {
    case DecodeAndConsist:
      /*
	if(dcc_data[1] == 0) 
	{
	if(!(config & (1<<RstFlag))) // Signal first Reset packet
	config |= (1<<RstFlag);
	else
	config |= (1<<SmPkt);      // Signal Service Mode
	return;                      // Return here to preserve RST and SM Semaphores
	}
      */
      if(dcc_data[1] == 1)
	  {
	    temp = cv2sram_offset(29);
        eeprom_write_byte(&temp,CV29initial);
        __init();                      // Hard Reset; ToDo: CV29=default
	  }
      break;
 
    case Rueckwaerts:
      config &= ~(1<<NewDir);
      break;
    case Vorwaerts:
      config |= (1<<NewDir);
      break;
      
    case Funktion1:
      /*
	The format of this instruction is 100DDDDD
	00001 --> CVs_ram[0]
	00010 --> CVs_ram[1]
	00100 --> CVs_ram[2]
	01000 --> CVs_ram[3]
	10000 --> CVs_ram[4]
      */
      temp1 = dcc_data[1];
      for(temp = num_base_cvs; temp <= num_cvs; temp += num_block_cvs)
	{
	  if(temp1 & (1<<0))
	  {
	   (CVs_ram[temp + PioConfig]) |= (1<<PORTSTATUS_BIT_POS);
	  }
      else
	  {
	   (CVs_ram[temp + PioConfig]) &= ~(1<<PORTSTATUS_BIT_POS);
	  }
	  temp1 >>= 1;  // Rotate the data byte
	}
      break;
      
    case Funktion2:
      /*
	This instruction has the format 101SDDDD
	S=0 -> F5-F8
	S=1 -> F9-F12
      */
      temp1 = NumOfFields;
      if(dcc_data[1] & (1<<5)) // F5-F8
	temp1 = 9;
 
      for(temp = num_base_cvs;temp < num_base_cvs + 4; temp++)
	{
	  if((dcc_data[1] & (1<<0)) && (temp1 + temp < NumIoPins))
	    {
		  (CVs_ram[temp + temp1 + PioConfig]) |= (1<<PORTSTATUS_BIT_POS);
		}
	      else
		{
	 	  (CVs_ram[temp + temp1 + PioConfig]) &= ~(1<<PORTSTATUS_BIT_POS);
		}
	  dcc_data[1] >>= 1;  // Rotate the data byte
	}
      break;
 
    case CVAccessFunc:
      /*
	{preamble} 0 [ AAAAAAAA ] 0 {instruction-bytes} 0 EEEEEEEE 1
	instruction bytes:
	Byte 1     Byte 2     Byte 3
	1110CCAA 0 AAAAAAAA 0 DDDDDDDD
	The defined values for Instruction type (CC) are:
	CC=00 Reserved for future use
	CC=01 Verify byte
	CC=11 Write byte
	CC=10 Bit manipulation
      */
      if((dcc_data[1] & 0x0C) == 4) // Verify
	{
	  if(dcc_data[3] == CVs_ram[cv2sram_offset(dcc_data[2] + 1)])
	    {
	      acknowledge();
	    }
	}
 
      if(config & (1<<SmPkt)) // Zweimal empfangen !
	{
	  if((dcc_data[1] & 0x0C) == 0xC) // Write
	    {
 
	      if(dcc_data[2] == 17 - 1) // Check that we receive CV17/CV18 paired
		{
		  cv17_scratch = dcc_data[3];
		  config1 |= (1<<CV17_Flag);
		}
	      if(dcc_data[2] == 18 - 1)
		{
		  cv18_scratch = dcc_data[3];
		  config1 |= (1<<CV18_Flag);
		}

	      if(dcc_data[2] == 30 - 1)
		{
		  neon_flash_on = dcc_data[3];
		}

	      if(dcc_data[2] == 31 - 1)
		{
		  neon_flash_off = dcc_data[3];
		}
 
	      if((config1 & (1<<CV18_Flag)) && (config1 & (1<<CV17_Flag)))
		{
		  eeprom_write_byte(&CVs_defaults[cv2sram_offset(17)] , cv17_scratch);
		  CVs_ram[cv2sram_offset(17)] = cv17_scratch;
		  eeprom_write_byte(&CVs_defaults[cv2sram_offset(18)] , cv18_scratch);
		  CVs_ram[cv2sram_offset(18)] = cv18_scratch;
		  config1 &= ~((1<<CV17_Flag) | (1<<CV18_Flag));
		  temp = cv2sram(29) | (1<<5); // Long Address Mode in CV29
		  eeprom_write_byte(&CVs_defaults[cv2sram_offset(29)] , temp);
		  config &= ~(1<<SmPkt);
		  goto ack_fn1;
		return;
		}
	      else if( !(config1 & (1<<CV18_Flag)) && (!(config1 & (1<<CV17_Flag))) )
		{
		  if(dcc_data[2] == 1 - 1) // Short Address Mode when CV1 is written
		    {
		      temp = cv2sram(29) & ~(1<<5);
		      eeprom_write_byte(&CVs_defaults[cv2sram_offset(29)] , temp);
		      CVs_ram[cv2sram_offset(29)] = temp;
		    }
		  CVs_ram[cv2sram_offset(dcc_data[2] + 1)] = dcc_data[3];
		  eeprom_write_byte(&CVs_defaults[cv2sram_offset(dcc_data[2] + 1)] , dcc_data[3] );
		  config &= ~(1<<SmPkt);
		ack_fn1:
		  acknowledge();
		}
	    }
	}
      else
	{
	  config |= (1<<SmPkt);  // Set CVacc semaphore
	  return; // Don't break. Return to save flag.
	}
 
      break;
 
    default:
      break;
    }
 
  //  decode_packet_multi_exit:
  config &= ~((1<<RstFlag) | (1<<SmPkt)); // Clear Semaphores if you came here
}
 
 
void decode()
{
  if( ! (dcc_data[0]^dcc_data[1]^dcc_data[2]^dcc_data[3]^dcc_data[4]^dcc_data[5])) // DCC XOR Check
    {
      if(cv2sram(29) & (1<<7))  // Multi Function or Accesseroy Mode ?
	{
	  // Accessory
	  if((((dcc_data[0] == 0b10111111) && ((dcc_data[1] & 0xF0) == 0x80)) ||   // 11bit Accessory Broadcast
	      (dcc_data[0] == cv2sram(1) && dcc_data[1] == cv2sram(9))) &&     // Compare Address 128-191 extended Accessory Decoder
	     (dcc_data[0] & (1<<7))) // MSB = 1
	    {
	      decode_packet_acc();
	      return;
	    }
	}
      else
	{
	  // Multi Function
	  if(((cv2sram(29) & (1<<5)) && (dcc_data[0] & 0xC0)) &&
	     (dcc_data[0] == cv2sram(17)) && (dcc_data[1] == cv2sram(18))) // 14 Bit
	    {
	      dcc_data[0] = dcc_data[1];
	      dcc_data[1] = dcc_data[2];
	      dcc_data[2] = dcc_data[3];
	      dcc_data[3] = dcc_data[4];
	      goto multi1;
	    }
	  else if ( (!(dcc_data[0] & (1<<7))) &&
		   (!(cv2sram(29) & (1<<5))) && (dcc_data[0] == cv2sram(1))) // 7 Bit
	    {
	      goto multi1;
	    }
 
	  if(dcc_data[0] == 0)  // Broadcast
	    {
	    multi1:
	      decode_packet_multi();
	      return;
	    }
	}
 
    }
}
 
//---------------------------------------------------------------------------------------------------------

#ifdef ATTiny44
void turnoff_porta(mask)
     unsigned char mask;
{
    PORTA &= ~mask;
}

void turnon_porta(mask)
     unsigned char mask;
{
    PORTA |= mask;
}
#endif

void turnoff_portb(mask)
     unsigned char mask;
{
  PORTB &= ~mask;
}

void turnon_portb(mask)
     unsigned char mask;
{
  PORTB |= mask;
}

void turnon(mask)
     unsigned char mask;
{
#ifdef ATTiny44
	 if(CVs_ram[step_io + PioConfig] & (1<<WHICHPORT_BIT_POS))
	 {
	   turnon_porta(mask);
	 }
	 else
	 {
	   turnon_portb(mask);
	 }
#endif

#ifdef ATTiny45
     turnon_portb(mask);
#endif
}

void turnoff(mask)
     unsigned char mask;
{
#ifdef ATTiny44
	 if(CVs_ram[step_io + PioConfig] & (1<<WHICHPORT_BIT_POS))
	 {
	   turnoff_porta(mask);
	 }
	 else
	 {
	   turnoff_portb(mask);
	 }
#endif

#ifdef ATTiny45
     turnoff_portb(mask);
#endif
}


void toggle(mask)
     unsigned char mask;
{
#ifdef ATTiny44
	 if((CVs_ram[step_io + PioConfig]) & (1<<WHICHPORT_BIT_POS))
	 {
	     if(PORTA & mask)
		 {
		    turnoff_porta(mask);
		 }
		 else
		 {
		    turnon_porta(mask);
		 }
	 }
	 else
	 {
	     if(PORTB & mask)
		 {
		    turnoff_portb(mask);
		 }
		 else
		 {
		    turnon_portb(mask);
		 }
     }
#endif

#ifdef ATTiny45
	     if(PORTB & mask)
		 {
		    turnoff_portb(mask);
		 }
		 else
		 {
		    turnon_portb(mask);
		 }
#endif
}




void work_io(void)
{
  unsigned char temp = (CVs_ram[step_io + PioConfig] >> 4) & 0xF;
  unsigned char temp1 = CVs_ram[step_io + PioPinnum]; // Bitmaske der PortPin Nummer
 
  // Configuration of IO Pin, Dimming, Neon, On/off etc. in low nibble
  // 0 -> Simple On/Off
  // 1 -> On/Off according to DIR
  // 2 -> Dimming
  // 3 -> Neon
  // 4 -> Blink
 
  switch(CVs_ram[step_io + PioConfig] & 0xF)
    {
    case 0: // Simple On/Off wird in DECODE gesetzt
      if(temp & (1<<PORTSTATUS))  // Check if Status is On/Off
	TURNON;
      else
	TURNOFF;
    break;

    case 1: // On/Off According to DIR, wird in DECODE gesetzt
     if(temp & (1<<PORTSTATUS))  // Check if Status is On/Off
      {
       if(config & (1<<NewDir))
	{
	  if(temp & (1<<WHICHDIR))
	    TURNON; // DDRB |= temp1;
	  else
	    TURNOFF;    // DDRB &= ~temp1;
	}
       if(!(config & (1<<NewDir)))
	{
	  if(!(temp & (1<<WHICHDIR)))
	    TURNON; // DDRB |= temp1;
	  else
	    TURNOFF;    // DDRB &= ~temp1;
	}
      }
     else
      {
       TURNOFF;
      }
    break;

    case 2: // Dimming
      if(!(temp & (1<<PORTSTATUS)))
	{
	  TURNOFF;
	  goto myexit;
	}
      DIM_DT_COUNTER++;
      if(PORTB & DIM_PINNUM)
	{
	  if(DIM_DT_COUNTER >= DIM_ON_TIME)
	    {
	      DIM_DT_COUNTER = 0;
	      TURNOFF;
	    }
	}
      else
	{
	  if(DIM_DT_COUNTER >= DIM_OFF_TIME)
	    {
	      DIM_DT_COUNTER = 0;
	      TURNON;
	    }
	}
    break;
 
    case 3: // Neon Count von 1 ist ca. 15,6 ms
      if(!(temp & (1<<PORTSTATUS)))
    {
	  TURNOFF;
	  NEON_STATE = 0; // Reset NEON state just in case ...
	  NEON_DELAY = 1;
	  goto myexit;
	}
      temp = NEON_STATE; // Neon Flash Status in CountHigh
      switch(temp)
	{
	case 0: // turn on first flash
	  NEON_COUNT = 0;
	  NEON_DELAY = 1;
	  NEON_STATE = 1; // next state
	  TURNON;
	  break;
	case 1:
	case 3:
	case 5:
	if(NEON_DELAY == 0)
	{
	  if(NEON_COUNT >= cv2sram(NEON_ON_CV))
	    {
	      NEON_COUNT = 0;
	      NEON_STATE++; // next state 2 or 4
	      TURNOFF;
	    }
	  NEON_COUNT++;
    }
	NEON_DELAY++;
	break;
	case 2:
	case 4:
	case 6:
	if(NEON_DELAY == 0)
	{
	  if(NEON_COUNT >= cv2sram(NEON_OFF_CV))
	    {
	      NEON_COUNT = 0;
	      NEON_STATE++; // next state 3
	      TURNON;
	    }
	  NEON_COUNT++;
    }
	NEON_DELAY++;
	break;
	default:
	  TURNON;
	  break;
	}
    break;
 
    case 4: // Blink. Count von 64 ist ca. 1Sek on, 1Sek off. also 2Sek tutto.
     if(!(temp & (1<<PORTSTATUS)))
	{
	  TURNOFF;
	  goto myexit;
	}
      BLINK_COUNT++;
      if(BLINK_COUNT == 0)
	{
	  BLINK_PWM--;
	  if(BLINK_PWM == 0)
	    {
	      BLINK_PWM = BLINK_FREQ; // Get Freq
          TOGGLE;
	    }
	}
    break;
    myexit:
    default: break;
    }
}
 
/*********************************************************************************/
 
/*
  DCCIN is sampled every 21us via TIMER0 Overflow Int. The DCC stream analysation is within this INT.
  A semaphore (Register config => GoDecode) is raised when a complete DCC packet is received.
  The Program jumps to the decoding routines.
*/
 
int main (void)
{
  unsigned char temp;
  eeprom_read_block(&CVs_ram,      &CVs_defaults, num_cvs); // Copy our setting to SRAM
 
#ifdef ATTiny45
  DDRB   = IO_DIR_Mask_PORTB;                        // Set Directions on Port B
#endif
 
#ifdef ATTiny44
  DDRB   = IO_DIR_Mask_PORTB;                        // Set Directions on Port B
  DDRA   = IO_DIR_Mask_PORTA;                        // Set Directions on Port A
#endif
 
 
  // Set TIMER0 for 21us sampling
  TCCR0A = (1<<WGM01) | (0<<COM0A1) | (0<<COM0A0);   // CTC Mode
  TCCR0B = (1<<CS00);                                // CTC Mode
  OCR0A  = 167;                                      // 21us Sample Rate at 8MHz Clock Speed
#ifdef ATTiny45
  TIMSK  = (1<<OCIE0A)+(0<<OCIE0B)+(0<<TOIE0);       // Set the OVF Int
#endif
 
#ifdef ATTiny44
  TIMSK0  = (1<<OCIE0A)+(0<<OCIE0B)+(0<<TOIE0);       // Set the OVF Int
#endif
 
  samples  = Abtast;
  state    = 0;
  bitrec   = 0;
  numbytes = 0;
  numbits  = 0;
  config   = 0;
  step_io  = num_base_cvs;
  neon_flash_on  = CVs_ram[cv2sram_offset(30)];
  neon_flash_off = CVs_ram[cv2sram_offset(31)];

  sei(); // Start receiving
 
  while(1)
    {
      work_io(); // Do the IO stuff
      step_io += num_block_cvs;
      if(step_io >= num_cvs)
	step_io = num_base_cvs;
 
      if(config & (1<<GoDecode)) // Decode ??
	{
	  // Don't messup our DCC command. Disable receiving here
	  cli();
	  // Clear 'DCC Packet ready' Semaphore
	  config &= ~((1<<GoDecode) | (1<<EndOfData));
	  // Reset samples, state and btirec container
	  samples = Abtast;
	  state   = 0;
	  bitrec  = 0;
	  // Clear rest of DCC array
	  for(temp = numbytes; temp <= 5; temp++)
	    dcc_data[temp] = 0;
	  // Go decoding
	  decode();
	  // Reset the receiving bits and pieces
	  numbytes = 0;
	  numbits = 0;
	  // Let Semaphores beeing explicitly handled by Sub-Routines
	  config &= ((1<<RstFlag) | (1<<SmPkt) | (1<<NewDir));
	  // Start receiving again
	  sei();
	}
    }
}